The present invention relates to a method of and apparatus for determining the integrity of a contact between an integrated circuit and a circuit board on which it is mounted. The method can be applied to complex circuit boards where many devices are in parallel.
The automatic testing of such board assemblies is common practice. CMOS and bipolar integrated circuits typically have parasitic or protection diodes between input and output pins and the device ground and power rails. This fact has been recognised and used in prior art testers to verify the integrity of component pin connections.
U.S. Pat. No. 5,280,237 and U.S. Pat. No. 6,188,235 take advantage of parasitic transistors formed in an integrated circuit by the parasitic diodes between the substrate and ground. Transistor tests are carried out in a ‘grounded-emitter’ configuration, and necessitate connection of device ground (GND) pins to a bias voltage, rather than to ground. Such tests are not possible to perform in situations where device ground pins are indeed connected to ground, as for example, may be the case with many commercial in-circuit testers.
U.S. Pat. No. 4,779,041 attempts to verify the presence of an internal common mode resistance connecting the diodes of each of two device pins and ground. A large current pulse applied to a second terminal causes a voltage drop across the inherent internal resistance, which then appears as a corresponding change in voltage at a first terminal subjected to a constant bias current The technique suffers from several disadvantages, including false readings due to multiple connected components sharing either or both of the pulse or bias currents, parallel current paths between the two pins under test due to other components, and external common mode resistance due to circuit board traces and connection to the tester. In addition, expected responses may vary considerably between devices of different batch or manufacturer.
U.S. Pat. No. 5,521,513 and U.S. Pat. No. 5,554,928 address some of the drawbacks of U.S. Pat. No. 4,779,041 by employing an alternative method of measuring the internal common mode resistance. A voltage source is connected simultaneously to two leads of a component, and the resultant current measured. The same voltage source then is connected to each of same two leads individually, and the resultant currents measured. The common resistance between the leads (and ground) may then be calculated from the resultant currents. Unfortunately, the use of a voltage stimulus presents a considerable problem in determining a suitable voltage level. The current resulting from applying a given voltage to a device pin may vary by orders of magnitude with that resulting from the exact same voltage applied to a different device pin, introducing uncertainties into operating conditions and expected responses.
U.S. Pat. No. 5,736,862 makes use of internal AC paths between pairs of integrated circuit pins. An AC signal applied to one pin will result in an output signal of the same frequency on a second pin when both pins are correctly connected. Another similar approach applies two AC signals having different frequencies to two device pins respectively, then utilizes the non-linear characteristic of forward-biased diodes to generate sum and difference frequencies, which may then be detected at a third device pin to deduce correct connection. The first method is susceptible to error signals due to parallel paths and external common mode resistance. The latter method is complicated through the necessary choice, biasing, and connection of, three individual device pins per test.
A related method “Analog AC Harmonic Analysis Method for Detecting Solder Opens” in the IEEE Proceedings of the International Test Conference 1997 (http://www.computer.org/proceedings/itc/4210/4210toc.htm) applies an AC signal to the first pin and measures the harmonic content of the output signal on a second pin of the same device, which reduces the number of undetected faults due to parallel paths.
EP 0,571,963 identifies multi-terminal structures formed by internal diodes between pins of similar functionality, being a general case of the parasitic transistors employed in U.S. Pat. No. 5,280,237. These structures are then biased so as to produce a set of terminal currents, which are then measured and subsequently compared, with marked variations being indicative of faulty connections. The demonstrated embodiment suffers from a problem associated with CMOS devices, being that of a large background current due to the additional parasitic diodes present between signal pins and the supply voltage pin (and addressed by U.S. Pat. No. 6,188,235). Once again, use of voltage biasing presents the problem of determining a suitable voltage for devices and pins having varying characteristics.
Each of the above techniques minimally requires two device pin connections, where the two chosen pins do not form part of the same bus, and may not both connect to pins of any other individual device. This requirement stems from the fact that, for these techniques, such parallel device connections tend to mask out the effects of any single device pin connect fault The resultant choice of two diversely functional pins may complicate selection of test stimuli, and make prediction of test response difficult or impossible.
Some methods advantageously compare results for pins within groups. The fact that these measurements have by necessity been made individually, and at separate times, introduces a measurement uncertainty, which may have considerable bearing on the integrity of test.
None of the above techniques explicitly address the problems associated with series resistance inherently present in the test path Any practical tester must electrically connect to the circuit board under test, usually using test wiring and probes, often in the form of a ‘bed-of-nails’. Such connections will have an associated series resistance, which can be both large and variable in magnitude, commonly due to probe pin or connector contact resistance. An undesired effect of such resistance is to introduce errors into both applied stimuli and measured responses, thereby significantly reducing the fidelity and consistency of test.
U.S. Pat. No. 5,365,180 presents a method for measuring the contact resistance between a probe card and the wafers onto which integrated circuits are fabricated, during wafer testing. A first and second test current are forced between two pins of the device under test through an isolating diode, and first and second resultant voltage drops measured respectively. A dynamic resistance is calculated by dividing the difference in measured voltages by the difference in test currents. The contact resistance may then be determined, for example, by subtracting a predetermined internal resistance value from the calculated dynamic resistance.
U.S. Pat. No. 5,786,700 similarly determines the linear interconnection resistance between two external access points of an electronic device. Various currents or voltages are injected between the two access points, so as to forward bias an internal ESD diode, and resultant voltages or currents measured. The resultant current-voltage relationships are applied to an interconnection model algorithm to yield an interconnection resistance.
Whilst the above two methods may be useful in determining values for dynamic and static series resistance, neither of these two quantities has any intrinsic importance in the detection of unconnected device pins, especially in cases having more than one device connection on a net.
Rather, it is desirable to detect pin connection failures reliably, in the presence of unknown series resistance in the test path.